Current Issue : April - June Volume : 2014 Issue Number : 2 Articles : 4 Articles
A wideband (0.8ââ?¬â??6GHz) receiver front-end (RFE) utilizing a shunt resistive feedback low-noise amplifier (LNA) and a micromixer\r\nis realized in 90nm CMOS technology for software-defined radio (SDR) applications.With the shunt resistive feedback and series\r\ninductive peaking, the proposed LNA is able to achieve a wideband frequency response in input matching, power gain and noise\r\nfigure (NF). A micromixer down converts the radio signal and performs single-to-differential transition. Measurements show the\r\nconversion gain higher than 17 dB and input matching (S11) better than -7.3 dB from 0.8 to 6GHz. The IIP3 ranges from -7 to\r\n-10 dBm, and the NF from 4.5 to 5.9 dB. This wideband receiver occupies 0.48mm2 and consumes 13mW....
This paper presents an ultrawideband low-noise amplifier chip using TSMC 0.18 Ã?µm CMOS technology. We propose a UWB low\nnoise amplifier (LNA) for low-voltage and low-power application.The present UWB LNA leads to a better performance in terms\nof isolation, chip size, and power consumption for low supply voltage. This UWB LNA is designed based on a current-reused\ntopology, and a simplified RLC circuit is used to achieve the input broadband matching. Output impedance introduces the LC\nmatching method to reduce power consumption. The measured results of the proposed LNA show an average power gain (S21) of\n9 dB with the 3 dB band from 3 to 5.6GHz. The input reflection coefficient (S11) less than -9dB is from 3 to 11GHz. The output\nreflection coefficient (S22) less than -8 dB is from 3 to 7.5GHz. The noise figure 4.6ââ?¬â??5.3 dB is from 3 to 5.6GHz. Input third-orderintercept\npoint (IIP3) of 2 dBm is at 5.3GHz. The dc power consumption of this LNA is 9mW under the supply of a 1V supply\nvoltage. The chip size of the CMOS UWB LNA is 1.03 Ã?â?? 0.78mm2 in total....
We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a\r\nprogrammable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can\r\nstore 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write\r\npulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required\r\nwhen using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell\r\nbefore the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we\r\nsimulated the effect of variations in the width of the transistor of the proposedMNV-SRAMcell, the resistance of the programmable\r\nresistor, and the power supply voltage with 180nm 3.3V CMOS HSPICE device models....
Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness (??SI) ranging from 46 nm\r\n(UTB scale) down to 1.6nm (NSB scale), were fabricated using a selective ââ?¬Å?gate recessedââ?¬Â process on the same silicon wafer. The\r\ngate-to-channel capacitance (????) and conductance (????) complementary characteristics, measured for NSB devices, were found to\r\nbe radically different from those measured for UTBS. Consistent ???? and ???? trends are observed by varying the frequency (??), the\r\nchannel length (??), and the channel thickness (??SI). In this paper, we show that these trends can be analyticallymodeled by amassive\r\nseries resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap\r\ndensity are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in\r\nwhich series resistance is of a great concern....
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